The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A digital clock signal (e.g., a digital clock signal used for timing functions, such as recovering timing of a read channel, in a hard disk drive) may be generated by interpolating an output of a voltage controlled oscillator (VCO) according to a digital phase adjustment provided by a timing loop. The digital clock signal may be required to operate within a range between a minimum clock rate (clockmin) and a maximum clock rate (clockmax). In other words, the digital clock signal may be required to be adjustable between clockmin and clockmax.
Typically, the VCO operates at a fixed frequency (i.e., the output of the VCO may have a fixed frequency fVCO), and/or changing the frequency of the output of the VCO may be difficult. Further, changing the frequency of the output of the VCO may introduce a transient in the output frequency. This transient is not appropriate for some applications, e.g., when a quick or even instantaneous frequency update is needed, or during ongoing read or write operations. Accordingly, a frequency offset Δf may be incorporated by the timing loop to change the rate of the digital clock signal without changing the frequency of VCO output.
FIG. 1 shows an example system 100 including a timing loop 104 (e.g., a digital portion of the system 100) that provides a digital phase adjustment to an analog portion 108 of the system 100. The analog portion 108 includes a VCO 112 that generates, based on an input voltage, an analog signal having a frequency fVCO. An interpolator 116 interpolates the analog signal according to a phase adjustment provided by the timing loop 104 to generate a digital clock signal having a desired phase and frequency.
The timing loop 104 (which corresponds to, for example only, a second order timing loop) receives a timing error e corresponding to a difference between a desired signal value and an actual signal value (e.g., of a signal corresponding to the digital clock signal generated by the interpolator 116). The timing error e includes each of phase error information and frequency error information associated with the digital clock signal. The timing loop 104 includes a frequency loop portion 120 and a phase loop portion 124.
The frequency loop portion 120 receives the timing error “e” as modified by a coefficient β, which is selected to convert the timing error e into a corresponding frequency error. For example, multiplier 128 multiplies the timing error e by the coefficient β. A frequency accumulator 132 generates a frequency offset Δf based on the frequency error, which is fed back to be summed with the frequency error by summer 136.
The phase loop portion 124 receives the timing error e as modified by a coefficient α, which is selected to convert the timing error e into a corresponding phase error. For example, multiplier 140 multiplies the timing error e by the coefficient α to generate phase error, which is summed with the frequency offset Δf at summer 144. A phase accumulator 148 generates an accumulated phase φ based on an output of summer 152, which sums the output of the summer 144, the output of the phase accumulator 148, and a zero phase start (ZPS) phase jump φZPS. The phase φ is provided to the interpolator 116 to adjust the phase of the digital clock signal. For example only, for a clock period T of the digital clock signal, increasing the phase φ may delay the digital clock signal (e.g., by up to 1 T). The achievable range for the frequency of the digital clock signal may correspond to [fVCO*(1+Δfmin), fVCO*(1+Δfmax)], where Δfmin and Δfmax correspond to a minimum frequency offset and a maximum frequency offset, respectively. Accordingly, the values Δfmin and Δfmax determine the ability of the timing loop to operate between the required minimum clock rate clockmin and maximum clock rate clockmax.
A (Zero Phase Start) ZPS module 156 generates the ZPS phase jump φZPS. For example, the ZPS module 156 generates the ZPS phase jump φZPS based on an evaluation of phase information of an underlying sinusoidal waveform. For example, one period of the sinusoidal waveform (e.g., corresponding to a read signal read from a storage medium of the HDD) includes four desired sampling points corresponding to a 0, a positive peak, a 0, and a negative peak. The ZPS module 156 performs the ZPS to cause the sampling phase to coincide with the desired sampling points of the sinusoidal waveform. For example, the ZPS module 156 may calculate a total phase jump value ψ, which may have a range of, for example only, [−1, 0] or [0, 1] (i.e., a total of 1 T). The total phase jump value ψ may be divided into N steps (i.e., N different phase jumps φZPS), where the sum of the N phase jumps equals the total phase jump value ψ (i.e., ψ=ΣφZPS). In other words, the ZPS module 156 outputs N phase jumps of φZPS to the summer 152 over N consecutive clock cycles to provide the total phase jump value ψ. Accordingly, if ψ is within the range of [0, 1] and N=4, then the range of each individual one of the N jumps φZPS may be in [0, ¼].